1. Field of the Invention
The present invention relates to a semiconductor integrated circuit lead frame which is to be mounted with a semiconductor chip and molded with a sealing resin.
2. Description of the Prior Art
FIG. 5 shows a conventional semiconductor integrated circuit lead frame of the above-mentioned type. A portion encircled by the dotted line in FIG. 5 and designated by numeral 6 is shown on a magnified scale in FIG. 6. A lead frame 200 has a chip mounting section 55 to be mounted with a semiconductor chip and a plurality of straight outer leads 56, 56, . . . which extend outwardly from the chip mounting section 55. A semiconductor chip mounted on the chip mounting section 55 is sealed with a sealing resin 60. The outer leads 56 are adapted to be electrically connected to the semiconductor chip.
The lead frame 200 further includes a plurality of dam bars 52 which are aligned in a direction perpendicular to the direction in which the outer leads 56 and 56 extend, and connect the adjacent outer leads 56. The dam bars 52 serve to dam off an excess sealing resin flowing over the chip mounting section 55 and leaking in between the outer leads 56 and 56 when the semiconductor chip is sealed with the sealing resin 60 on the chip mounting section 55. When the sealing resin 60 is solidified, the dam bars 52 have completed their duties, and therefore punching regions 70 of the dam bars 52, which are shown in FIG. 7, are punched out to disconnect the outer leads 56 from each other.
FIG. 9 shows a further prior art lead frame which is disclosed in Japanese Patent Laid-open Application No. 2-244750 (published in 1990). Note that in FIG. 9, parts similar to those in FIGS. 5-7 are indicated by the same reference numerals. In the lead frame of FIG. 9, alternate dam bars (tiebars), indicated by reference characters X and Y, are formed in different positions and connect the adjacent straight outer leads (external leads) 56 which extend outwardly from the chip mounting section (resin mold section) 55.
In accordance with the recent trend of increasing the integration or packing density of semiconductor integrated circuits and enhancing the function of each semiconductor chip, the pitch of the outer leads is being subject to reduction.
In the above-described prior art lead frames, according as the pitch of the outer leads 56 is reduced, the size of the dam bar 52, X, Y is necessarily reduced. In practice, when the outer lead pitch is 0.5 mm, the outer lead width is 0.2 mm and the inter-lead dimension of the dam bar provided between the outer leads is 0.3 mm according to EIAJ (Electronic Industries Association of Japan). A die for punching the dam bars of 0.3 mm is required to be designed to have a blade width of 0.24 mm when a tolerance in positioning the blades is .+-.30 .mu.m. When the outer lead pitch is further reduced to 0.3 mm, the outer lead width is 0.12 mm and the inter-lead dimension of the dam bar provided between the adjacent outer leads is 0.18 mm according to the EIAJ. Then, a die for punching the dam bars of 0.18 mm is required to be designed to have a blade width of 0.12 mm when a tolerance in positioning the blades is .+-.30 .mu.m. As obvious from the above, when the outer lead pitch is reduced from 0.5 mm to 0.3 mm, the blade width of the die for punching the dam bars is required to be reduced to one half so long as the fabrication technique and the assembling technique are on the same levels. The blade pitch is also reduced.
Unfortunately, according as the blade width is reduced, the abrasion resistance of the blades is deteriorated and the wearing speed of the blades is increased. This results in an increased rate of occurrence of damages. Furthermore, according as the blade width and the blade pitch are reduced, it is getting more difficult to position the blades, i.e., to align the blades with the dam bars, with precision in the punching process of the dam bars.